Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation
by Kanchan Manna; Chakradhar Reddy Veeramreddy; Santanu Chattopadhyay; Indranil Sengupta
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 5, No. 3, 2015

Abstract: This paper presents a thermal-aware test scheduling strategy for cores in a network-on-chip (NoC) design. NoC infrastructure has been utilised to transport test data, thus, avoiding hardware overhead for testing. The scheme is capable of exploiting the capabilities of cores to operate at different frequencies to leverage in testtime and power. Thermal behaviour of the NoC has been modelled using a simple strategy based on core powers and floorplan, thus, avoiding the necessity to perform costly thermal simulations in the schedule generation process. The model has been integrated with a particle swarm optimiser to identify a set of solutions with trade-off in testtime, peak temperature and temperature variance of the NoC. Experimental results show that the testtime results are comparable to the existing power-constrained multifrequency approaches. While the existing approaches produce single result, the proposed approach can produce a range of results. It shows significant improvements in terms of testtime compared to the other reported approaches taking either power or peak temperature as a constraint.

Online publication date: Sat, 04-Jul-2015

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