Fault-tolerant architecture for serial-parallel multipliers
by Aida O. Abd El-Gawad
International Journal of Computer Applications in Technology (IJCAT), Vol. 11, No. 1/2, 1998

Abstract: An efficient fault-tolerant architecture for use in serial-parallel multipliers is proposed. This architecture uses a time redundancy method together with the technique of a fast serial-parallel multiplier to achieve both error detection and error location with small time and hardware overheads. The design is most suitable for use in VLSI circuits and digital signal processing applications where serial data is available.

Online publication date: Sun, 01-Jun-2014

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