A low power, low jitter DLL based low frequency (250 kHz) clock generator
by P. Ghosal; H. Rahaman; Koyel Mukherjee; Dibyendu Ballabh
International Journal of Signal and Imaging Systems Engineering (IJSISE), Vol. 7, No. 1, 2014

Abstract: Digital Delayed Locked Loop (DLL)-based clock generation has proven itself a viable alternative in today's clock design segment over the traditional Phase Locked Loop (PLL)-based design by offering lower design complexity with satisfying low power budget. In this paper, a novel design of an on-chip clock generator of very low frequency of 250 kHz and 50% duty cycle using a DLL has been presented. The worst-case jitter produced by the clock is only 11.3 ns. The clock has rise time and fall time of 164.39 ps and 123.7 ps (on an average), respectively, with a glitch of 6 mV. The clock produces a very low power of 3.92 mW. The design was implemented under 180 nm process technology and assuming 1.8 V power supply.

Online publication date: Fri, 24-Oct-2014

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