Maximising area-constrained partial fault tolerance in reconfigurable logic using selection criteria Online publication date: Sat, 19-Jul-2014
by David L. Foster; Darrin M. Hanna
International Journal of Embedded Systems (IJES), Vol. 5, No. 1/2, 2013
Abstract: As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a number of methods of fault tolerance have been developed to ensure reliable operation. Most current techniques output the required circuit area based on the desired level of fault tolerance with some techniques increasing the area by over 200%. In deployed systems, however, the FPGA is fixed and the area available for adding fault tolerance is limited. As a consequence, protecting an updated, larger circuit using the same fault tolerance scheme may result in a design that no longer fits in the deployed FPGA. This situation dictates the need for area-aware techniques that can trade fault tolerance for lower area penalties. The open question with these approaches is partitioning the circuit into protected and unprotected subsets to maximise the fault coverage. This paper presents several methodologies for selecting subsets and analyses their performances on several circuits based on fault coverage provided, additional latency, and running times.
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