Monitoring transaction level SystemC models using a generic and aspect-oriented framework Online publication date: Sat, 16-Aug-2014
by Meriam Kallel; Younes Lahbib; Adel Baganne; Rached Tourki
International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 4, No. 3, 2012
Abstract: Transaction level modelling (TLM) is gaining acceptance as a way to create hardware designs at high abstraction levels. It allows better simulation performances and early prototyping for system-on-chip (SoC) designs. Transaction level models are therefore increasingly being used as golden references. In this paper, we present a new framework for the verification of properties of SystemC transaction level models during simulation. Functional as well as performance properties are addressed. Aspect-oriented programming (AOP) techniques are exploited to monitor the design under verification in an automated way and to write assertion checkers that fit TLM requirements. In addition, we propose a generic SystemC implementation approach that allows the specification and validation of fully-parameterisable transaction level properties. We illustrate our work on a realistic multi-level SoC platform based on the TLM-2.0 standard and including Open Core Protocol (OCP) interfaces.
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Computer Aided Engineering and Technology (IJCAET):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email subs@inderscience.com
Our Blog 
Follow us on Twitter 
Visit us on Facebook