Efficient don't care filling and scan chain masking for low-power testing
by Subhadip Kundu; Santanu Chattopadhyay
International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 4, No. 2, 2012

Abstract: This paper addresses two methods for reducing power consumption during testing. The first one is to assign suitable values to the unspecified bits (don't cares) in the test patterns so that both static and dynamic power are reduced. The second technique discusses the issue of blocking pattern selection for reducing power consumption during circuit testing in a scan-based approach. The blocking pattern is used to prevent the scan chain transitions from reaching circuit inputs. This, though reduces dynamic power significantly, can result in quite an increase in the leakage power. We have presented a novel approach to select a blocking pattern using genetic algorithm and use it properly so that both dynamic and leakage power are reduced.

Online publication date: Sat, 16-Aug-2014

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