Architecture synthesis methodology for cost-effective run-time reconfigurable systems
by Pil Woo Chun, Lev Kirischian
International Journal of Embedded Systems (IJES), Vol. 4, No. 3/4, 2010

Abstract: Run-time reconfiguration of field programmable devices can change their internal structure and behaviour in response to dynamic requests. Thus, reconfigurable systems with programmable fabrics can offer a cost effective solution to address the multi functionalities of today's applications. This paper recognises the cost benefits that such run-time adaptability can provide and proposes a novel reconfigurable architecture synthesis methodology to achieve a cost-effective reconfigurable system solution. The proposed architecture synthesis methodology converts a recognised dynamic environment into an assembled micro-level system. New design steps of the methodology identify a multi-task and multi-mode workload, determine an appropriate reconfiguration granularity and synthesise a workload-specific static architecture for a run-time reconfigurable system that enables on-chip assembly of pre-constructed components. The experimental results show the cost benefits of the proposed methodology which saves 73% of area and 29.8% of power compared to fixed design approach for implementing multiple visual processors.

Online publication date: Fri, 11-Mar-2011

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