Reconfigurable processor based on ALU array architecture for software radio
by Makoto Ozone, Tatsuo Hiramatsu, Katsunori Hirase, Kazuhisa Iizuka, Shin-ichiro Tomisawa
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 3, No. 1, 2011

Abstract: We have developed an original reconfigurable processor LSI for software radio systems for consumer products. The die size of the LSI is 5.65 mm by 5.65 mm. The processor is based on ALU array architecture and has original limitations on connections of ALUs. The circuit size is small because of the limitations. It achieves high processing performance by processing multiple threads simultaneously. We have developed a prototype of a broadcasting receiver with the LSIs. The prototype has realised the real-time reception of three kinds of broadcasts by changing software using a maximum of two LSIs. We also have estimated a power consumption of the LSI and have confirmed that power consumption can be reduced by approximately 55% of that of the LSI. By doing so, we have advanced a realisation of software radio for consumer products.

Online publication date: Sat, 21-Mar-2015

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