FPGA implementation of area–time efficient CORDIC processor dedicated to compute exponentials in neural networks
by Supriya Aggarwal, Kavita Khare
International Journal of Signal and Imaging Systems Engineering (IJSISE), Vol. 3, No. 4, 2010

Abstract: This paper presents high-performance exponential computation based on the Coordinate Rotation Digital Computer (CORDIC) algorithm with emphasis on minimum hardware requirements. The redesigned unified CORDIC algorithm provides high throughput and is beneficial for the VLSI implementation of the activation functions in neural networks and realisation of exponent calculations in Gaussian Potential Functions (GPFs). Ease of design and scale-free operation of the proposed technique extend the range of convergence compared with the original CORDIC algorithm. Approximately, 57.1% hardware savings are accomplished in comparison with Flat CORDIC architectures for 32-bit word-length. The word-length of the processor is extendible and the experimental results confirm its efficacy.

Online publication date: Mon, 10-Jan-2011

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