Verification and implementation of software for dependable controllers
by Krzysztof Sacha
International Journal of Critical Computer-Based Systems (IJCCBS), Vol. 1, No. 1/2/3, 2010

Abstract: A method is described for modelling, verification and automatic generation of code for PLC controllers. The requirements for a controller are modelled using UML state machine diagram, with a formal semantics given by a finite state time machine. The model can automatically be converted into a timed automaton, embedded into a model of the environment (a controlled plant) and verified against safety requirements using UPPAAL – a free model checking tool for the networks of timed automata. The verified model can automatically be translated into a program code in one of the IEC 61131 languages, e.g., ladder diagram of structured text.

Online publication date: Sun, 21-Feb-2010

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