Fast fault-tolerant adders
by Janusz Biernat
International Journal of Critical Computer-Based Systems (IJCCBS), Vol. 1, No. 1/2/3, 2010

Abstract: Several measures can be undertaken to achieve fault-tolerance of arithmetic devices. They differ in the level of hardware redundancy and the coverage of detectable faults. The discussion of the possible solutions for fast fault tolerant adders is given in the paper. The hardware complexity growth and latency overhead of various designs with respect to fault-coverage is discussed in the paper. It is shown that the designs of fast fault-tolerant adders based on the concept of residue code or double-rail code are preferable.

Online publication date: Sun, 21-Feb-2010

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