A hardware-in-the-loop simulation environment for real-time systems development and architecture evaluation Online publication date: Sun, 21-Feb-2010
by Vasily V. Balashov, Anatoly G. Bakhmurov, Maxim V. Chistolinov, Ruslan L. Smeliansky, Dmitry Y. Volkanov, Nikita V. Youshchenko
International Journal of Critical Computer-Based Systems (IJCCBS), Vol. 1, No. 1/2/3, 2010
Abstract: In this paper, we present a technology for integration of distributed real-time embedded systems (RTES) based on hardware-in-the-loop simulation. The environment to support this technology is described. This environment also enables simulation-based development of RTES software and evaluation of RTES architecture on early stages of RTES development.
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Critical Computer-Based Systems (IJCCBS):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email subs@inderscience.com