Compact FPGA-based systolic array architecture suitable for vision systems
by Griselda Saldana, Miguel Arias-Estrada
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 1, No. 2, 2007

Abstract: Motion estimation is a very computational demanding operation during video compression process in standards such as MPEG4, thus special hardware architectures are required to achieve real-time compression performance. The present work focuses on the development of a reconfigurable systolic-based architecture implementing the Full Search Block Matching Algorithm (FBMA) which is highly computing-intensive and requires a large bandwidth to obtain real-time performance. The architecture comprises a smart memory scheme to reduce the number of accesses to data memory and Router elements to handle data movement among different structures inside the same architecture, adding the possibility of chaining interconnection of multiple processing blocks. Every Processing Element (PE) in the array includes a double ALU in order to search multiple macroblocks in parallel. The functionality has been extended to support operations involved in some other low-level image algorithms. Results show that a peak performance in the order of 9 GOPS can be achieved.

Online publication date: Sun, 14-Oct-2007

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