Limits for a feasible speculative trace reuse implementation
by Mauricio L. Pilla, Bruce R. Childers, Felipe M.G. Franca, Amarildo T. Da Costa, Philippe O.A. Navaux
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 1, No. 1, 2007

Abstract: Trace reuse is a powerful technique to dynamically collapse instructions. Traces, that is, dynamic sequences of instructions, are detected during runtime and their inputs and outputs are stored in a table. The next time the same address is reached and the inputs are the same, this sequence of instructions can be safely bypassed and the same outputs are written in registers and memory. One of the major issues with trace reuse is that all inputs must be ready for the reuse test or the trace cannot be reused. Reuse through Speculation on Traces (RST) adds value prediction to trace reuse, so that traces with inputs that are not ready for early validation can be speculatively reused and validated later in the pipeline. Another important problem is the number of wires that are used to transmit inputs from the reuse table to the reuse test stage, which increases with table associativity and pipeline width. In this paper, we compare the limits of RST with two reuse implementation strategies: one with two reuse tables and high associativity and another with a direct-mapped, unified reuse table. The unified table organisation, considerably simpler to implement, presented a speedup of 1.24 over the baseline with a reduction of less than 4% in performance when compared to the two table approach.

Online publication date: Thu, 19-Apr-2007

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