An asynchronous and parallel row-wise compressed SpMV kernel on heterogeneous CPU-GPU architectures
by Huachen Tan
International Journal of Embedded Systems (IJES), Vol. 15, No. 5, 2022

Abstract: Sparse matrix vector multiplication (SpMV) is a fundamental and important algebra used extensively in various fields, such as machine learning, data mining and numerical simulation. Accelerating SpMV benefits the corresponding real-world applications. Meanwhile, heterogeneous CPU-GPU architectures are inevitable to realise high-performance computing. Therefore, this paper designs an asynchronous parallel row-wise compressed SpMV kernel by utilising the heterogeneous CPU-GPU architectures to accelerate applications that use SpMV. First, according to the memory access and control flow of SpMV and the architectural features of the heterogeneous CPU-GPU systems, the heterogeneous parallelisation of the row-wise compressed SpMV based on CSR format is designed. Next, an asynchronous method is designed for the parallel compressed SpMV kernel to create an additional level of parallelism in SpMV execution. The proposed SpMV kernel can obtain up to 8.97% improvement from the asynchronous method on the heterogeneous CPU-GPU architecture and perform the nearly linear speedup across GPU threads.

Online publication date: Wed, 23-Nov-2022

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