SVM-based current ripple reduction with two parallel interleaved inverters for induction motor drive Online publication date: Mon, 31-Oct-2022
by Ranvir Kaur; Gursewak Singh Brar; Maninder Kaur
International Journal of Power Electronics (IJPELEC), Vol. 16, No. 4, 2022
Abstract: Extensive research has been ongoing in the field of inverter fed induction motor drives. The main challenge in designing pulse width modulation (PWM) fed induction motor drives is to reduce total harmonic distortion (THD) and ripple content in AC output of inverter. The PWM method ensures the voltage balancing between two parallel interleaved inverter (PII) inverters for each switching cycle. The PII includes two parallel units of two level three-phase PWM full bridge having multiple carrier waves with phase rotation analysed as single unit of three-level inverter. PII improves the performance of drive while employing space vector modulation (SVM) by reducing THD content by 14% for low modulation indices and improves up to 40% at high modulation indices. Ripple content is significantly reduced in line current for PII. Simulation and experimental results for PII for 5 hp induction motor are presented in this paper to validate low ripple current at output.
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