Performance parameter analysis and estimation of high-K induced three-fin SOI n-FinFET at 14 nm gate length
by Rudra Sankar Dhar; Sumit Kumar Sinha; Abhishek Verma; Taniya Chowdhury; Harshit Singh Tomar; Swagat Nanda; Zohmingmawia Renthlei
International Journal of Nanoparticles (IJNP), Vol. 14, No. 2/3/4, 2022

Abstract: The FinFET performances started degrading below the 32-nm technology node as a consequence of shrinking gate oxide thicknesses below 2 nm. Thus, the inclusion of high-k dielectric materials as gate oxides has become pivotal for efficient suppression of short channel effects (SCEs). Although the incorporation of high-k materials has diminished leakage currents, the drive currents have also lessened. It is observed that increasing the number of fins in the device significantly enhances the drain current. This paper describes the implementation of a 3-fin tri-gate (TG) SOI FinFET structure with high-k dielectric materials like Si3N4, Al2O3, ZrO2 and HfO2 replacing SiO2 as gate oxide. An effective oxide thickness (EOT) of 1 nm is considered for the study of the electrical characteristics of all the devices. It was established that the use of 3-fin structure notably enhanced the drive currents while HfO2 decreased the leakage currents leading to excellent switching speeds of the FinFET structure.

Online publication date: Mon, 24-Oct-2022

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