High-speed pre-accumulator and post-multiplier for convolution neural networks with low power consumption
by K. Mariya Priyadarshini; R.S. Ernest Ravindran; M. Sujatha; K.T.P.S. Kumar
International Journal of Internet Protocol Technology (IJIPT), Vol. 15, No. 3/4, 2022

Abstract: In today's phase of growing technology Convolution Neural Networks (CNNs) are all over the places. It is a thriving segment in machine learning and Artificial Intelligences (AI) techniques. CNN needs bulk amount of computing competence and memory with higher frequency range. In this present investigation, Pre-Accumulator and Post-Multipliers (PAPM) are proposed which accelerate the speed of processor. 4-bit multiplier using Carry Save Adder (CSA) is built with 6Transistors-Adder and sutras of Vedic mathematics is constructed. Accumulator of multiplier and accumulator are designed with Two Level Edge Triggering Flip-Flops (TLET-FF) to increase bandwidth of the memory. The proposed architecture of Multiply Accumulate (MAC) circuit consumes very less power when compared to existing high speed MACs. Performance of accumulator is contrasted with three different, two-level triggered flip-flops namely 16TLET-FF, 14TLET-FF and 12TLET-FFs. The projected MAC replaces the existing multipliers due its low power together with high frequency of operation.

Online publication date: Wed, 05-Oct-2022

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