Implementation of area-efficient AES using FPGA for IOT applications Online publication date: Fri, 09-Sep-2022
by Muttuluru Sreekanth; R.K. Jeyachitra
International Journal of Embedded Systems (IJES), Vol. 15, No. 4, 2022
Abstract: The increase in internet technology has made the number of devices connected to the internet increase day by day. The information transferred over the electronic media is vulnerable to security attacks. To protect the information, the data transferred over the internet should be encrypted. Therefore, it is essential to design the encryption architecture which is suitable for the resource constrained devices. FPGA implementation of area-efficient AES encryption algorithm is presented in this work. The proposed architecture includes 8-bit data path which reduces the number of internal wires. There are two register banks, the state register and the key register, which are used for storing intermediate results along with performing the operations in encryption and key expansion phase which reduces the area. Substitute bytes operation is implemented using ROM based LUT structure. The mix columns operation with 8-bit data path is realised using the four internal registers. This reduces area which is suitable for IOT applications which is the primary objective.
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