Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks Online publication date: Fri, 09-Sep-2022
by Vivek Kumar Singh; Abhishek Nag; Sambhu Nath Pradhan
International Journal of Embedded Systems (IJES), Vol. 15, No. 4, 2022
Abstract: This paper presents an efficient and dynamic approach to a dual gating strategy in finite state machines (FSMs) to reduce the overall power dissipation. The FSMs are implemented in configurable logic blocks (CLBs) of an FPGA, and the gating criteria are derived from the self-loop information within the FSM. Fine-grained power gating may cause practical mistakes in CLB functioning, resulting in data loss. As a result, in addition to power gating, a clock gating approach is proposed to maintain data at the output of power gated CLBs. The simulations were conducted for standard MCNC benchmark circuits implemented in CLBs, designed and simulated in the 45 nm technology CADENCE tool, resulting in an overall 25.82% power savings at the cost of excess look up table (LUT) utilisation within CLBs. As the complexity of the FSM increases, the excess LUT utilisation associated with this methodology decreases.
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