Design of energy and EDP efficient 1-bit full subtractor based divider circuits for computing systems Online publication date: Mon, 14-Mar-2022
by M. Mahaboob Basha; Srinivasulu Gundala; Sibghatullah I. Khan
International Journal of System of Systems Engineering (IJSSE), Vol. 11, No. 3/4, 2021
Abstract: In today's very large scale integration (VLSI) systems, energy efficiency, power consumption per clock frequency is major concern in SoC designs. The two performance parameters, namely, the power and delay, which generally make a decision regarding energy metric of the system. In this paper, a 10T (Transistor) full subtractor is proposed and compared between various one bit full subtractor (OBFS) circuits with fewer transistor count. From the results, it is observed that, the proposed 10T OBFS circuit achieves savings of more than 48% in delay, 49% in energy consumption, and 74% in energy delay product (EDP) when compared with complementary metal oxide semiconductor (CMOS) transistor scheme and 20T OBFS. Similarly, the 14T OBFS circuit achieves savings of more than 40% in power, energy consumption, and EDP when compared with the 10T OBFS scheme and other designs. The proposed 10 transistor full subtractor based divider circuit is power, energy, and EDP efficient.
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