Automatic generation of VHDL code for a railway interlocking system
by Martín N. Menéndez; Santiago Germino; Facundo S. Larosa; Ariel Lutenberg
International Journal of Embedded Systems (IJES), Vol. 14, No. 6, 2021

Abstract: This article introduces a novel technique to automatically analyse a railway network geographical representation and produce a suitable FPGA railway interlocking system by generating its VHDL hardware description. This approach accelerates the design, implementation and testing phases on different topologies. We review the automated tools developed - which are part of a comprehensive workflow - and present the results for topologies of varying complexities.

Online publication date: Thu, 24-Feb-2022

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