Multithreading on reconfigurable hardware: a performance evaluation approach of a multicore FPGA architecture
by George K. Adam
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 10, No. 2, 2021

Abstract: This paper addresses the performance issues of multiple threads running on a multithreaded field programmable gate array (FPGA) multicore architecture, supported by a real-time variant of Linux operating system. The objective is to investigate the efficiency of running in parallel and concurrently multithreaded applications and evaluate performance metrics including execution time, speedup, response latency, and CPU and memory usage. The development platform is a 16-core architecture implemented with Nios II soft processors on an ALTERA Cyclone IV FPGA. Performance is analysed and evaluated based upon the development and implementation of an iterative algorithm for the generation and execution of multithreaded tasks. Experimental tests were executed in a number of cores configurations and threads combinations under different workloads, such as matrix multiplication and read-write operations on on-chip memory. The results confirm the validity of the proposed approach in running and evaluating efficiently multithreaded tasks in real-time with noticeable performance improvements in terms of timing features.

Online publication date: Thu, 25-Nov-2021

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