Effective hardware architectures for LED and PRESENT ciphers for resource-constrained applications
by Piyush Modi; Pulkit Singh; Bibhudendra Acharya
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 10, No. 2, 2021

Abstract: Existing cyber physical systems (CPS) and internet-of-things (IoT) services depend largely on the widespread implementation of tiny smart devices for tracking, storing, monitoring, and networking applications. All IoT-enabled devices, including consumer smart devices, need secure communication mechanisms. In this paper, three different architectures are proposed based on LED and PRESENT lightweight block ciphers targeting at resource-constrained applications. This paper discusses two specific hardware architectures for the LED cipher. The first architecture introduces a round-based pipelined design in which pipeline registers are inserted in between round operations. Whereas the second is a serialised architecture that runs on a single cell per clock cycle. These proposed designs offer very efficient area-throughput tradeoff. In addition, we proposed a 32-bits datapath optimisation design to achieve high-performance, low-power, and energy-efficient hardware of PRESENT cipher encryption system. Various field programmable gate array (FPGA) platforms are used for hardware implementation and results are evaluated and compared with other related works.

Online publication date: Thu, 25-Nov-2021

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