FPGA implementation of polar codes for 5G eMBB control channels Online publication date: Wed, 24-Nov-2021
by G. Aparna; Raparla Swathi; M. Kezia Joseph; C.N. Sujatha; B. Rajendra Naik
International Journal of Ultra Wideband Communications and Systems (IJUWBCS), Vol. 4, No. 3/4, 2021
Abstract: The rapid growth in wireless communications and information technology over a decade is demanding advanced wireless technologies development. Design and implementation of channel codes for different code lengths (N) and varying code rates (R) to handle the latency and the hardware requirements for enhanced mobile broad band (eMBB) control channel standards like 5G is a challenging issue at present. Polar codes are treated as a solution to the above defined design aspects to fulfil the requirements by the 3rd Generation Partnership Project (3GPP). Therefore, a VLSI architecture for polar codes implementation using SCLD method based on LLR approach is designed and simulated using VHDL programming, ISE Navigator 14.2, HDL synthesiser on the target FPGA device XC6vlx760-1-ffl760 for analysing various code lengths N [128, 256, 512] as inputs and code rates R [1/6, 1/3, 1/2] in this paper.
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