Methods of automatic testing the very large integrated circuit of memory Online publication date: Wed, 13-Oct-2021
by K.K. Smirnov; A.V. Nazarov; V.V. Blinov
International Journal of Nanotechnology (IJNT), Vol. 18, No. 9/10, 2021
Abstract: The paper describes the methods of designing test solutions, that include a set of tests and electrical equipment for testing a very large scale integrated (VLSI) circuit of memory. A route is presented for the automatic solution of this problem in the FT Studio software and hardware environment, which operates on the basis of the object and machine-oriented language STeeL. The FT Studio software and hardware complex allows you to automate the verification of almost all types of VLSI, the composition of which is determined by current standards. The functioning of the complex is based on the two-way communication of the mathematical and topological models of VLSI, which is constantly maintained in real time when performing the technological process of functional control of the VLSI RAM. To identify hidden defects in memory cells in the STeeL language, a special memory component is implemented. Its application allowed significantly to reduce the preparation time of test solving for testing VLSI of memory.
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