A low power architecture for 1D median filter using carry look ahead adder Online publication date: Thu, 16-Sep-2021
by Sharana Basappa; P. Ravi Babu
International Journal of Advanced Intelligence Paradigms (IJAIP), Vol. 20, No. 1/2, 2021
Abstract: In image and signal processing applications, it is very essential to suppress the noisy signal while protecting the required information. In this paper, one dimensional median filter is used to reduce the energy per sample (EPS). Median filter is one of the fundamental and best building blocks in many image processing applications. This median filter design will be implemented in VLSI architecture to find hardware utilisation, and cost. In this paper, low cost carry look-ahead adder median filter (LC-CLA-MF) method is introduced to improve the speed of median filter architecture. Area, power, delay will be analysed for 5 windows and 9 windows for 8-bit and 16-bit median filter architecture using 180 nm technology. In FPGA implementation, LUT, number of slices, flip flops, and frequency will be analysed for different Virtex devices. Finally, area, power, delay, area power product (APP) and area delay product (ADP) will be minimised in LC-CLA-MF method than conventional method.
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