MPI hardware framework for many-core based embedded systems
by Rodrigo Vinicius Mendonça Pereira; Laio Oriel Seman; Marcelo Daniel Berejuck; Douglas Rossi De Melo; Analucia Schiaffino Morales; Eduardo Augusto Bezerra
International Journal of Sensor Networks (IJSNET), Vol. 35, No. 1, 2021

Abstract: This paper presents an investigation and evaluation of the services and infrastructure performance of a software and hardware implementation subset of the message passing interface (MPI) standard. The proposal for an efficient MPI Hardware and MPI Software models, along with the presentation and evaluation of its queuing model, aims at giving the system design a framework to assist. Comparative results are presented between MPI in hardware and software such as silicon consumption, processing time and transfer rate of the system related to the size of buffers. Tests in an environment consisting of an MPSoC model integrated on a network-on-chip (NoC) were performed, including classical algorithms such as PI calculation and the Dining Philosophers problem, to evaluate the proposed model functionality. Experimental results demonstrated the effectiveness of the proposed approach and the resulting implementation, although this comes at the cost of increased use of silicon in hardware implementation.

Online publication date: Mon, 08-Feb-2021

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