A new parallel DSP hardware compatible algorithm for noise reduction and contrast enhancement in video sequence using Zynq-7020
by Madhura Shivaraju; Suresh Krishnappa
International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 13, No. 1/2, 2020

Abstract: Various video processing applications such as liquid crystal display processing, high quality video photography, terrestrial video recording and medical imaging systems requires robust noise reduction and contrast enhancement technique which provides visually pleasing for real time implementation novel hardware architecture has been designed using look-up-table (LUT) acceleration approach which helps achieve high speed processing. Until now, a lot of researchers have worked on noise removal and contrast enhancement of digital videos, but the developed algorithms works with only some verity of noises and failed to produce desirable results for various types of distortions and real time implementation is still remaining a challenge. Hence, appropriate filter needs to be designed which address both kinds of errors. In this paper, adaptive trilateral filter has been designed for noise reduction the results are measured using qualitative and quantitative analysis which has aided in better utilisation of hardware for real time implementation. The experimental results show that the proposed algorithm provides a frame rate of 40 fps on an average and has a resolution of 720 × 576. The proposed algorithm was implemented on ZedBoard Znyq-7020 development kit by Xilinx.

Online publication date: Fri, 03-Jul-2020

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