Overlapping memory operations with circuit evaluation in reconfigurable computing
by Yosi Ben-Asher, Daniel Citron, Gadi Haber
International Journal of Embedded Systems (IJES), Vol. 2, No. 1/2, 2006

Abstract: This paper considers the problem of compiling programs, written in a high-level programming language, into hardware circuits executed by an Field Programmable Gate Array (FPGA). In particular, we consider the problem of synthesising nested loops that frequently access array elements stored in an external memory (outside the FPGA). We propose an aggressive profile-based compilation scheme, based on loop unrolling and code flattening techniques, where array references from/to the external memory are overlapped with an uninterrupted hardware evaluation of the synthesised loop's circuit. Experimental results show that large code segments can be compiled into circuits by using the proposed scheme.

Online publication date: Wed, 05-Jul-2006

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