Performance analysis and design optimisation of 3-⌀ Packed U Cell inverter for industrial drive applications
by Rajanand Patnaik Narasipuram; Ravindranath Tagore Yadlapalli
International Journal of Mathematical Modelling and Numerical Optimisation (IJMMNO), Vol. 9, No. 3, 2019

Abstract: Nowadays, the importance for multilevel inverters is getting more and more in the field of medium and high power applications. This paper discusses Packed U Cell (PUC) multilevel inverter which is the most advanced topology. The figure of merit of this topology is reduction in the number of switches as level increases. Hence, it reduces the cost implementation besides topology complexity compared to other existing topologies such as neutral-point clamping (NPC), flying capacitor (FC), cascaded H-bridge (CHB) and hybrid cascaded H-bridge (HCHB). Furthermore, there is no need of transformers in this whole concept. Hence, it avoids the bulky installations. The 3-⌀ induction motor is fed with 7, 15 and 31 levels Packed U Cell (PUC) inverter topologies individually. The stator current, speed response and electromagnetic torque is shown for each level. The performance of induction motor is analysed in terms of % torque ripples and % total harmonic distortion (%THD). The whole simulations are carried out by using MATLAB/Simulink version R2012b.

Online publication date: Sat, 29-Jun-2019

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