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Title: |
Off-loading application controlled data prefetching in numerical codes for multi-core processors |
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Author: |
J. Weidendorfer, C. Trinitis 
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Address: |
Institut fur Informatik, Technische Universitat Munchen, D-85747 Garching bei Munchen, Germany. ' Institut fur Informatik, Technische Universitat Munchen, D-85747 Garching bei Munchen, Germany |
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Journal: |
International Journal of Computational Science and Engineering 2008 - Vol. 4, No.1 pp. 22 - 28 |
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Abstract: |
An important issue when designing numerical code in High Performance Computing is cache optimisation in order to exploit the performance potential of a given target architecture. This includes techniques to improve memory access locality as well as prefetching. Inherent algorithm constrains often limit the first approach, which typically uses a blocking technique. While there exist automatic prefetching mechanisms in hardware and/or compilers, they can not complement blocking with additional prefetching. We provide an infrastructure for off-loading application controlled prefetching on a chip multiprocessor, allowing to further improve numerical code already optimised by standard cache optimisation. Clear benefits are shown for real workloads on existing hardware. |
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Keywords: |
chip multiprocessing; multi-core processors; cache optimisation; data prefetching; numerical codes; high performance computing. |
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DOI: |
10.1504/IJCSE.2008.021109 |
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