An efficient implementation of FPGA based high speed IPSec (AH/ESP) core Online publication date: Fri, 08-Jun-2018
by Muzaffar Rao; Thomas Newe; Edin Omerdic; Gerard Dooly; Elfed Lewis; Daniel Toal
International Journal of Internet Protocol Technology (IJIPT), Vol. 11, No. 2, 2018
Abstract: The IPSec is used to secure the IP traffic. The IPSec protocol was designed to fulfil the need to provide security at the network level, so that all the higher-layer protocols in the OSI model could take advantage of it. The implementation of IPSec is a computationally heavy task that affects the high speed network performance. To overcome this issue, the best possible solution is hardware implementation. For a hardware implementation the FPGA platform is considered as one of the best solutions because of its re-configurability and high performance capabilities. The work presented here gives a complete FPGA based implementation of IPSec. This includes both (AH and ESP) IPSec protocol formats. Both IPSec formats are implemented using transport mode and tunnel mode operations. IPSec is not bounded to use any specific cryptographic algorithms; here IPSec is used with the AES and SHA-3 algorithms to provide confidentiality and integrity services respectively.
Online publication date: Fri, 08-Jun-2018
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Internet Protocol Technology (IJIPT):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email firstname.lastname@example.org