A novel method for reduction of leakage current in MOSFET Online publication date: Fri, 06-Apr-2018
by Debasis Mukherjee; B.V. Ramana Reddy
International Journal of Convergence Computing (IJCONVC), Vol. 3, No. 1, 2018
Abstract: In this paper, structural modification of conventional bulk MOSFET has been proposed for minimisation of subthreshold leakage current. Key structural features of bulk MOSFET have been kept unaltered. Comparison of conventional and proposed structure has been presented for a 20 nm NMOS with 0.8 volt Vdd. The proposed structure is capable of reducing subthreshold leakage current even at very low drain voltage when the gate voltage is zero. Around 55% reduction of OFF current has been obtained when drain voltage is at Vdd and gate voltage is zero. The methodology proposed does not have any special requirement at the circuit level, and can be combined with all circuit level methodologies. The proposed structure is named as 'defensive MOSFET' as it looks like a defensive shield. Structural dimensions of 20 nm MOSFET generation have been taken from the 2011 edition of International Technology Roadmap for Semiconductors or ITRS. All simulation processes have been executed by Sentaurus G-2012.06 Technology Computer Aided Design or TCAD software.
Online publication date: Fri, 06-Apr-2018
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Convergence Computing (IJCONVC):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email firstname.lastname@example.org