Novel concept for reducing the power consumption of look ahead carry adder circuit by using stackiabatic technique
by Kapil Mangla; Anil Kumar
International Journal of Autonomic Computing (IJAC), Vol. 2, No. 4, 2017

Abstract: For many years, designing of the high speed low power circuits with CMOS technology was a difficult challenge for the research community. There are various levels at which design problem related to low power and increased demand can be addressed; these levels are - software level, architecture level, algorithm level, circuit level and process technology level. In this paper, we have designed a four-bit look ahead carry adder using CMOS technology. The objective of this paper is to search for different approaches that will reduce the consumption of power of look ahead carry adder. We have designed look ahead carry adder using stackiabatic technique and compared with conventional, adiabatic and stacking techniques.

Online publication date: Wed, 31-Jan-2018

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

 
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Autonomic Computing (IJAC):
Login with your Inderscience username and password:

    Username:        Password:         

Forgotten your password?


Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com