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A platform based SOC design methodology and its application in image compression
by Kai-Yuan Jan, Chih-Bin Fan, An-Chao Kuo, Wen-Chi Yen, Youn-Long Lin
International Journal of Embedded Systems (IJES), Vol. 1, No. 1/2, 2005
Abstract: We describe a platform based design methodology for system-on-a-chip (SOC). An embedded 32-bit RISC CPU and a field-programmable gate array (FPGA) are used to implement applications that require both a program running on the CPU and hardware acceleration performed by the FPGA. The methodology consists of flow and tools for hardware/software partitioning, hardware accelerator design/synthesis, software compilation, interface generation, integrated hardware/software cosimulation, and system verification. We also present a case of implementing an image decoder in a hardware/software codesign fashion on the platform. Experimental results show that the methodology is indeed effective for IP development/verification and fast prototyping.
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