A compact model for electrostatic discharge protection nanoelectronics simulation
by Hung-Mu Chou, Shao-Ming Yu, Jam-Wem Lee, Yiming Li
International Journal of Nanotechnology (IJNT), Vol. 2, No. 3, 2005

Abstract: In nanoelectronics, snapback phenomena play an important role in electrostatic discharge (ESD) protection devices, in particular for gigascale, very large scale integration (VLSI) circuit design. In this paper we present a new ESD equivalent circuit model for deep submicrion and nanoscale semiconductor device simulation. By considering the geometry effect in the formulation of snapback characteristics, our model can be directly incorporated into electronic circuit simulation for the whole chip ESD protection circuit design. With the developed ESD model, we can investigate robust enhancement problems and perform a SPICE based whole chip ESD protection circuit design in nanoelectronics.

Online publication date: Fri, 11-Nov-2005

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Nanotechnology (IJNT):
Login with your Inderscience username and password:

    Username:        Password:         

Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com