Reconfigurable multi-core architecture - a plausible solution to the von Neumann performance bottleneck Online publication date: Wed, 27-Jan-2016
by Chun-Hsien Lu; Chih-Sheng Lin; Hung-Lin Chao; Jih-Sheng Shen; Pao-Ann Hsiung
International Journal of Adaptive and Innovative Systems (IJAIS), Vol. 2, No. 3, 2015
Abstract: The ill-famed von Neumann bottleneck has been the main performance hurdle since the invention of computers. Although several techniques such as separate data/instruction caches, branch prediction, and parallel computing have been proposed and improved efficiency, the throughput bottleneck between CPU and memory is still very much there. We propose a novel reconfigurable multi-core architecture (RMA) to address this issue via the dynamic allocation of heterogeneous computing resources and distributed memory. We show how this is feasible with the state-of-the-art technologies of dynamic partial reconfiguration of hardware resources and runtime operating system configuration. Experiments and analysis show how RMA alleviates the performance bottleneck.
Online publication date: Wed, 27-Jan-2016
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