An evolvable hardware system in Xilinx Virtex II Pro FPGA Online publication date: Wed, 25-Apr-2007
by Zdenek Vasicek, Lukas Sekanina
International Journal of Innovative Computing and Applications (IJICA), Vol. 1, No. 1, 2007
Abstract: In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs). Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution by Martinek and Sekanina, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 sec in average.
Online publication date: Wed, 25-Apr-2007
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