Diminution of power in load/store queue for CAM and SRAM-based out-of-order processors
by G. Dhanalakshmi; M. Sundarambal; K. Muralidharan
International Journal of Advanced Intelligence Paradigms (IJAIP), Vol. 15, No. 1, 2020

Abstract: In a modern world for non numeric applications, out-of-order super scalar processors are designed to achieve higher performance. Unfortunately the improvement in the performance has lead to the increase in the chip power and energy dissipation. The load/store queue is a one of the major power consuming unit in the data path design during dynamic scheduling. Load/store queue is designed to absorb busts in cache access and maintain the order of memory operations by keeping all in-flight memory instruction in program order. The proposed technique aims at reducing both dynamic and static power dissipation in the load/store queue (LQ/SQ) by using power-gating technique and priority encoder. Through this implementation, the least amount of redesign, verification efforts, lowest possible design risk, least hardware overhead is achieved without significant impact on the performance.

Online publication date: Sat, 07-Dec-2019

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Advanced Intelligence Paradigms (IJAIP):
Login with your Inderscience username and password:

    Username:        Password:         

Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com