International Journal of Embedded Systems

This journal also publishes Open Access articles

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Editor in Chief: Prof. Kuan-Ching Li
ISSN online: 1741-1076
ISSN print: 1741-1068
6 issues per year
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Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from vehicles, telephones, audio-video equipment, aircraft, toys, security systems, medical diagnostics, to weapons, pacemakers, climate control systems, manufacturing systems, intelligent power systems etc. IJES addresses the state of the art of all aspects of embedded computing systems with emphasis on algorithms, systems, models, compilers, architectures, tools, design methodologies, test and applications.

 



 Topics covered include

  • Embedded systems architecture
  • Embedded software and hardware
  • Application-specific processors/devices
  • Embedded cybersecurity and cryptography
  • Real-time systems
  • Hardware/software co-design
  • Testing techniques
  • Industrial practices, benchmark suites
  • Internet of Things (IoT) technologies and applications
  • Emerging technologies/applications/principles
  • Embedded machine learning, deep learning and artificial Intelligence

 

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Embedded System Architecture:

  • Heterogeneous multiprocessors, reconfigurable platforms, memory management support, communication, protocols, network-on-chip, real-time systems, and embedded microcontrollers, etc.

Embedded Software:

  • Compilers, assemblers and cross-assemblers, programming, memory management, object-oriented aspects, virtual machines, scheduling, concurrent software for SoCs, distributed/resource aware OS, OS and middleware support, etc.

Embedded Hardware:

  • System-on-a-chip, DSPs, hardware specification, synthesis, modelling, simulation and analysis at all levels for low power, power-aware, testable, reliable, verifiable systems, performance modelling, validation, security issues, real-time behaviour, and safety critical systems, etc.

Application-specific Processors and Devices:

  • Network processors, real-time processor, media and signal processors, application-specific hardware accelerators, reconfigurable processors, low power embedded processors, bio/fluidic processors, bluetooth, handheld devices, flash memory chips, etc.

Real-time Systems:

  • All real-time related aspects such as software, parallel and distributed real-time systems, real-time kernels, real-time OS, task scheduling, multitasking design, etc.

Hardware/Software Co-design:

  • Methodologies, test and debug strategies, real-time systems, interaction between architecture and software design, specification and modelling, design representation, synthesis, partitioning, estimation, design space exploration beyond traditional hardware/software boundary, theory and algorithms, etc.

Testing Techniques:

  • All aspects of testing, including design-for-test, test synthesis, built-in self-test, and embedded test, for embedded and system-on-a-chip systems.

Industrial Practices and Benchmark Suites:

  • System design, processor design, software, tools, case studies, trends, emerging technologies, experience maintaining benchmark suites, representation, interchange format, copyrights, maintenance, reference implementations, and metrics, etc.

Embedded System Education:

  • Courses, textbooks, teaching tools and methods.

Emerging New Topics:

  • New challenges for next generation embedded computing systems, arising from new technologies (e.g., nanotechnology), new applications (e.g., pervasive or ubiquitous computing, embedded internet tools), new principle (e.g., embedded engineering), etc.

 

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Objectives

The objective of IJES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on embedded systems.


Readership

Scientists, engineers, researchers, graduate students, educators, managers and industrial professionals.


Contents

IJES is a refereed international journal providing an international forum to report, discuss and exchange experimental or theoretical results, novel designs, work-in-progress, experience, case studies, and trend-setting ideas. Papers should be of a quality that represents the latest advances in embedded systems in time-to-market, cost, code size, weight, testability, power, real-time behaviour, and stimulating future trends.


 

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Vol. 9
Vol. 8
Vol. 7
Vol. 6
Vol. 5
Vol. 4

 

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 IJES is indexed in:

 

 IJES is listed in:

 

Editor in Chief

  • Li, Kuan-Ching, Providence University, Taiwan
    (journaleditorialmanager@outlook.com)

      Executive Editor

      • Zhou, Qingguo, Lanzhou University, China

      Associate Editors

      • Ben Abdallah, Abderazek, University of Aizu, Japan
      • Giorgi, Roberto, Università degli Studi di Siena, Italy
      • Li, Jin, Guangzhou University, China
      • Liu, Chen, Clarkson University, USA
      • Marino, Mario Donato, Leeds Beckett University, UK
      • Thampi, Sabu M., Indian Institute of Information Technology and Management - Kerala (IIITM-K), India
      • Vaidyanathan, R. (Vaidy), Louisiana State University, USA

      Advisory Board

      • Bertino, Elisa, Purdue University, USA
      • Cao, Jiannong, Hong Kong Polytechnic University, Hong Kong SAR, China
      • Chapman, Barbara, Stony Brook University, USA
      • Gao, Guang R., University of Delaware, USA
      • Gaudiot, Jean-Luc, University of California – Irvine, USA
      • Guo, Minyi, Shanghai Jiao Tong University, China
      • Hwang, Kai, University of Southern California, USA
      • King, Chung-Ta, National Tsing Hua University, Taiwan
      • Lee, Jenq-Kuen, National Tsing Hua University, Taiwan
      • Li, Keqin, State University of New York at New Paltz, USA
      • Li, Keqiu, Tianjin University, China
      • Prasanna, Viktor K., University of Southern California, USA
      • Serikawa, Seiichi, Kyushu Institute of Technology, Japan
      • Wang, Cho-Li, The University of Hong Kong, Hong Kong SAR, China
      • Xu, Zhiwei, Chinese Academy of Sciences, China
      • Xue, Jingling, University of New South Wales, Australia
      • Yang, Laurence T., St Francis Xavier University, Canada
      • Zheng, Si-Qing, University of Texas at Dallas, USA
      • Zima, Hans, California Institute of Technology, USA

      Editorial Board Members

      • Amato, Flora, University of Naples "Federico II", Italy
      • Arabnia, Hamid R., University of Georgia, USA
      • Bertogna, Marko, University of Modena, Italy
      • Brito, Alisson, Universidade Federal da Paraíba, Brazil
      • Chen, Jian-Jia, Technische Universität Dortmund, Germany
      • Chen, Wen Zhi, Zhejiang University, China
      • Cheng, Albert M.K., University of Houston, USA
      • Cohen, Albert, INRIA, France
      • Colace, Francesco, University of Salerno, Italy
      • Dobre, Ciprian, University Politehnica of Bucharest, Romania
      • Ficco, Massimo, Second University of Naples, Italy
      • Guo, Bing, Sichuan University, China
      • Hsiung, Pao-Ann, National Chung Cheng University, Taiwan
      • Htike, Kyaw Kyaw, UCSI University, Malaysia
      • Huang, Kuo-Chang, National Taichung University, Taiwan
      • Jararweh, Yaser, Jordan University of Science and Technology, Jordan
      • John, Lizy Kurian, University of Texas at Austin, USA
      • Li, Haohan, Google Inc. , USA
      • Lin, Man, St. Francis Xavier University, Canada
      • Lo Bello, Lucia, University of Catania, Italy
      • Manimaran, Govindarasu, Iowa State University, USA
      • Marques, Eduardo, University of São Paulo, Brazil
      • Morón, Célio Estevan, Universidade Federal de São Carlos - UFSCar, Brazil
      • Moscato, Vincenzo, National Interuniversity Consortium for Informatics (Consorzio CINI), Italy
      • Mosse, Daniel, University of Pittsburgh, USA
      • Ota, Kaoru, Muroran Institute of Technology, Japan
      • Pereira, Monica, Universidade Federal do Rio Grande do Norte, Brazil
      • Pop, Paul, The Technical University of Denmark (DTU), Denmark
      • Rui, Zhou, Lanzhou University, China
      • Sato, Liria Matsumoto, University of Sao Paulo, Brazil
      • Shen, Jian, Nanjing University of Information Science and Technology, China
      • Srimani, Pradip K., Clemson University, USA
      • Susilo, Willy, University of Wollongong, Australia
      • Tumeo, Antonino, Pacific Northwest National Laboratory, USA
      • Wang, Chien-Min, Academia Sinica, Taiwan
      • Wang, Guojun, Guangzhou University, China
      • Xie, Yi, Xiamen University, China

       

      A few essentials for publishing in this journal

       

      • Submitted articles should not have been previously published or be currently under consideration for publication elsewhere.
      • Conference papers may only be submitted if the paper has been completely re-written (more details available here) and the author has cleared any necessary permissions with the copyright owner if it has been previously copyrighted.
      • All our articles go through a double-blind review process.
      • All authors must declare they have read and agreed to the content of the submitted article. A full statement of our Ethical Guidelines for Authors (PDF) is available.
      • There are no charges for publishing with Inderscience, unless you require your article to be Open Access (OA). You can find more information on OA here.

       

      Submission process

       

      All articles for this journal must be submitted using our online submissions system.

      Read our preparing and submitting articles page.

       

       

      Journal news

      • Forthcoming paper

         

        Title: GO-CP-ABE: group-oriented ciphertext-policy attribute-based encryption
        Authors: Yang Li, Xiaoling Tao, Wei Wu, Joseph K. Liu
        Abstract: This paper introduces a variant of ciphertext-policy attribute-based encryption called Group-Oriented Ciphertext-Policy Attribute-Based Encryption (GO-CP-ABE). In the new notion, a message is encrypted under an access structure over attributes and users are described by their attributes. In addition, users are divided into different groups and each user belongs to only one group. Users within the same group can merge their attributes to decrypt successfully, if the union of their attributes satisfies the access structure embedded in the ciphertext. But users from different groups can not realise this cooperative decryption. We define the security model of GO-CP-ABE and present an efficient design by revising an existing CP-ABE scheme.

        More details...

      • Forthcoming paper

         

        Title: Area coverage estimation model for directional sensor networks
        Authors: Zhimin Liu, Weijia Jia, Guojun Wang
        Abstract: Recently, directional sensor networks (DSNs) have received a great deal of attention owing to their wide range of applications in different fields. A directional sensor has a smaller angle of sensing range than an omni-directional sensor. Coverage is one of the fundamental problems of directional sensor networks at present, which reflects how well the environment is monitored. In this paper, we propose a coverage estimation model to estimate the coverage problem with boundary effect. In order to guide initial deployment of DSNs and better meet requirements with certain initial coverage probability effectively, a novel probability-based area coverage estimation model with boundary effect, named PCPMB, is proposed. Simulation results show that our proposed model outperforms the previous proposed model without boundary effect.

        More details...

      • Forthcoming paper

         

        Title: Multi-core model checking and maximum satisfiability applied to hardware-software partitioning
        Authors: Alessandro Trindade, Renato Degelo, Edilson Galvo, Hussama Ismail, Helder Silva, Lucas Cordeiro
        Abstract: Bounded Model Checking (BMC) based on Satisfiability Modulo Theories (SMT) is well known by its capability to verify software. However, its use as an optimisation tool, to solve hardware and software (HW-SW) partitioning problems, is something new. In particular, its integration with the maximum satisfiability solver vZ tool, which provides a portfolio of approaches for solving linear optimisation problems over SMT formulas, is unprecedented. We present new alternative approaches to solve the HW-SW partitioning problem. First, we use SMT-based BMC in conjunction with a multi-core support using open multi-processing to create four variants to solve the partitioning problem. The multi-core SMT-based BMC approaches allow initialising many verification instances based on the number of available processing cores, where each instance checks a different optimum value until the optimisation problem is satisfied. Additionally, we integrate the vZ into the BMC, making it as a specialised solution for optimisation in a single-core environment. We implement all five approaches on top of the Efficient SMT-Based Context-Bounded Model Checker (ESBMC) and compare them with a state-of-the-art optimization tool. Experimental results show that there is no single optimisation tool to solve all HW-SW partitioning benchmarks, but based on medium-size benchmarks, ESBMC-vZ had better performance.

        More details...