International Journal of High Performance Systems Architecture (IJHPSA)

International Journal of High Performance Systems Architecture

2016 Vol.6 No.1

Special Section Editorial

Pages Title and author(s)
1-12On the effectiveness of accelerating MapReduce functions using the Xilinx Vivado HLS tool
Mageda Sharafeddin; Mazen A.R. Saghir; Haitham Akkary; Hassan Artail; Hazem Hajj
DOI: 10.1504/IJHPSA.2016.076197
13-27KUMMS: optimising DRAM locality with Kernel-user behaviours
Beilei Sun; Xi Li; Chao Wang; Bo Wan; Xuehai Zhou
DOI: 10.1504/IJHPSA.2016.076202

Special Section on Innovative Design Method for Smart Concurrent Systems

28-35Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs
Burhan Khurshid; Roohie Naaz
DOI: 10.1504/IJHPSA.2016.076205
36-50Slider: an online and active deadlock avoider by serial execution of critical sections
Zhen Yu; Xiaohong Su; Peijun Ma
DOI: 10.1504/IJHPSA.2016.076193
51-60Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams
J.P. Anita; P. Sudheesh
DOI: 10.1504/IJHPSA.2016.076204