International Journal of High Performance Systems Architecture
2015 Vol.5 No.3
Pages | Title and author(s) |
127-140 | Pipelined hardware design of self tuning controller with on-chip parameter estimatorS.P. Joy Vasantha Rani DOI: 10.1504/IJHPSA.2015.070384 |
141-152 | Thermal-aware multifrequency network-on-chip testing using particle swarm optimisationKanchan Manna; Chakradhar Reddy Veeramreddy; Santanu Chattopadhyay; Indranil Sengupta DOI: 10.1504/IJHPSA.2015.070385 |
153-165 | New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sourcesShirin Rezaie; Reza Faghih Mirzaee; Keivan Navi; Omid Hashemipour DOI: 10.1504/IJHPSA.2015.070387 |
166-177 | Improving Map-Reduce for GPUs with cacheArun Kumar Parakh; M. Balakrishnan; Kolin Paul DOI: 10.1504/IJHPSA.2015.070392 |
178-191 | Execution time optimisation using delayed multidimensional retimingYaroub Elloumi; Mohamed Akil; Mohamed Hedi Bedoui DOI: 10.1504/IJHPSA.2015.070393 |