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Vol. 1

International Journal of High Performance Systems Architecture

2007 Vol. 1 No. 2

Special Issue on Reconfigurable and Scalable High Performance Architectures

Guest Editor: Nader Bagherzadeh

 

Editorial
PagesTitle and authors
79-88A flexible processor for the characteristic 3 ηT pairing
Robert Ronan, Colin Murphy, Tim Kerins, Colm O.hEigeartaigh, Paulo S.L.M. Barreto
DOI: 10.1504/IJHPSA.2007.015393

89-97Reconfiguration support for vector operations
Hongyan Yang, Sotirios G. Ziavras, Jie Hu
DOI: 10.1504/IJHPSA.2007.015394

98-105Design of a router for network-on-chip
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
DOI: 10.1504/IJHPSA.2007.015395

106-112Efficient finite field processor for GF(2163) and its implementation
Bijan Ansari, Huapeng Wu
DOI: 10.1504/IJHPSA.2007.015396

113-123An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip
Muhammad Ali, Michael Welzl, Sven Hessler, Sybille Hellebrand
DOI: 10.1504/IJHPSA.2007.015397

124-132Compact FPGA-based systolic array architecture suitable for vision systems
Griselda Saldana, Miguel Arias-Estrada
DOI: 10.1504/IJHPSA.2007.015398

133-142SPA resistant elliptic curve cryptosystem using addition chains
Andrew Byrne, Francis Crowe, William Peter Marnane, Nicolas Meloni, Arnaud Tisserand, Emanuel M. Popovici
DOI: 10.1504/IJHPSA.2007.015399