Title: Hardware implementation of multi-objective differential evolution algorithm: a case study of spectrum allocation in cognitive radio networks

Authors: Kiran Kumar Anumandla; Rangababu Peesapati; Samrat L. Sabat

Addresses: Department of Electrical Engineering, Indian Institute of Technology Hyderabad, Hyderabad 502285, India ' Department of Electronics and Communication Engineering, National Institute of Technology Meghalaya, Shillong, Meghalaya 793003, India ' Centre for Advanced Studies in Electronics Science and Technology, University of Hyderabad, Telangana 500046, India

Abstract: In this paper, a hardware solution for multi-objective differential evolution (MODE) algorithm is presented. The proposed hardware is developed as a co-processor and interfaced with PowerPC440 processor of Virtex-5 field programmable gate array to accelerate execution speed on an embedded platform. It is validated by optimising four standard benchmark functions and its execution time is compared with the same algorithm running on a 32-bit PowerPC440 processor. Further, as a case study, the proposed hardware is used to solve Spectrum Allocation (SA) problem in Cognitive Radio Network (CRN). In CRN, the available licensed channels are assigned to cognitive users using SA task while satisfying the multiple objectives posed by licensed users. The MODE core is integrated with the SA objective functions and developed as a MODE-based SA (MODE-SA) co-processor on an embedded platform for distributed CRN. The MODE-SA core has attained a speedup of 50-60× compared to the PowerPC440 implementation.

Keywords: FPGA; multi-objective differential evolution; MODE; hardware accelerator; spectrum allocation; cognitive radio; system on chip; Pareto front; network utility functions; auxiliary processor unit.

DOI: 10.1504/IJICA.2017.088176

International Journal of Innovative Computing and Applications, 2017 Vol.8 No.4, pp.241 - 253

Received: 27 Jun 2016
Accepted: 06 Apr 2017

Published online: 27 Nov 2017 *

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