Title: ChronoSym: a new approach for fast and accurate SoC cosimulation

Authors: Iuliana Bacivarov, Aimen Bouchhima, Sungjoo Yoo, Ahmed A. Jerraya

Addresses: SLS Group, TIMA Laboratory, 46 Av. Felix Viallet, 38031 Grenoble, France. ' SLS Group, TIMA Laboratory, 46 Av. Felix Viallet, 38031 Grenoble, France. ' CAE Center, SoC R&D lab. System LSI, Semiconductor Business, Samsung Electronics, Soowon, Korea. ' SLS Group, TIMA Laboratory, 46 Av. Félix Viallet, 38031 Grenoble, France

Abstract: The early validation of modern SoC is not anymore feasible using traditional cycle-accurate cosimulations. These are based on the concurrent execution between SW running on multiple Instruction Set Simulators and HW simulators. The challenge is then speeding-up the simulation, without sacrificing the accuracy of traditional methods. The key contribution of this paper is a novel fast and accurate HW/SW cosimulation approach, allowing to handle large SoCs, while reducing the design cycle. The key underlying concepts are timed native SW execution, combined with detailed HW/SW interaction models. This approach is implemented in ChronoSym tool and applied to two real SoC applications.

Keywords: SoC validation; SOC verification; hardware-software cosimulation; HAL simulation model; timed native execution; timing accuracy; system-on-chip; embedded systems; SOC design.

DOI: 10.1504/IJES.2005.008812

International Journal of Embedded Systems, 2005 Vol.1 No.1/2, pp.103 - 111

Published online: 26 Jan 2006 *

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