Title: A platform based SOC design methodology and its application in image compression

Authors: Kai-Yuan Jan, Chih-Bin Fan, An-Chao Kuo, Wen-Chi Yen, Youn-Long Lin

Addresses: Department of Computer Science, National Tsing Hua University, Hsin-Chu, 30043 Taiwan, ROC. ' Department of Computer Science, National Tsing Hua University, Hsin-Chu, 30043 Taiwan, ROC. ' Department of Computer Science, National Tsing Hua University, Hsin-Chu, 30043 Taiwan, ROC. ' Department of Computer Science, National Tsing Hua University, Hsin-Chu, 30043 Taiwan, ROC. ' Department of Computer Science, National Tsing Hua University, Hsin-Chu, 30043 Taiwan, ROC

Abstract: We describe a platform based design methodology for system-on-a-chip (SOC). An embedded 32-bit RISC CPU and a field-programmable gate array (FPGA) are used to implement applications that require both a program running on the CPU and hardware acceleration performed by the FPGA. The methodology consists of flow and tools for hardware/software partitioning, hardware accelerator design/synthesis, software compilation, interface generation, integrated hardware/software cosimulation, and system verification. We also present a case of implementing an image decoder in a hardware/software codesign fashion on the platform. Experimental results show that the methodology is indeed effective for IP development/verification and fast prototyping.

Keywords: system-on-chip; silicon intellectual property; hardware-software co-design; FPGA; field programmable gate arrays; fast prototyping; JPEG; discrete cosine transform; hardware accelerator; embedded systems; SOC design; platform based design; image decoder; system verification; simulation.

DOI: 10.1504/IJES.2005.008806

International Journal of Embedded Systems, 2005 Vol.1 No.1/2, pp.23 - 32

Published online: 26 Jan 2006 *

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