Int. J. of High Performance Systems Architecture   »   2017 Vol.7, No.2

 

 

Title: An enhanced model for reliable deflection routing in mesh network on chip

 

Authors: Simi Zerine Sleeba; M.G. Mini

 

Addresses:
Department of Electronics, Government Model Engineering College, Kochi, Kerala, India
College of Engineering, Cherthala, Kerala, India

 

Abstract: Massive integration of processing cores into a finite chip area increases the possibility of damage and failure of various chip components. Issues and solutions related to reliable on chip communication is of great importance in this context. On chip routers play a vital role in routing packets through the NoC. In this paper, we propose a new fault tolerant routing model for NoCs using deflection routing mechanism. This model intelligently utilises fault-free unidirectional links between the routers to forward flits to their destinations in a few number of hops. These links are activated at regular time intervals so that they serve as alternate productive paths for flits which are delayed due to faults in their computed routes. We also present a routing algorithm that exploits the path diversity in the network generated by the enhanced model. From experimental analysis, we obtain significant improvement in the network performance parameters like flit latency, deflection rate and dynamic energy dissipation across router links for the proposed model compared to the state-of-the-art fault tolerant routing methods in NoC.

 

Keywords: network on chip; fault tolerant routing; deflection routing; average latency; dynamic link energy; enhanced model; reliability; fault rate; output port allocation; buffer-less router; link fault; active input/ouput ports.

 

DOI: 10.1504/IJHPSA.2017.10008113

 

Int. J. of High Performance Systems Architecture, 2017 Vol.7, No.2, pp.87 - 97

 

Date of acceptance: 24 Apr 2017
Available online: 02 Oct 2017

 

 

Editors Full text accessPurchase this articleComment on this article