Article: A 12T MT-CMOS low power and low leakage SRAM cell Journal: International Journal of Computer Aided Engineering and Technology (IJCAET) 2017 Vol.9 No.3 pp.307 - 323 Abstract: This paper focuses on the design of low power and stable, novel 12T multi-threshold CMOS (MTCMOS)-based static random access memory (SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines. Reduction in swing voltage reduces the dynamic power dissipation. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep-to-active (OFF-to-ON condition) and active-to-sleep (ON-to-OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. So in the proposed SRAM cell both dynamic and static powers have been reduced. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. The circuit simulation has been done in 45 nm CMOS environment. Microwind 3.1 is used for the purpose of schematic and layout designs. Inderscience Publishers - linking academia, business and industry through research

Title: A 12T MT-CMOS low power and low leakage SRAM cell

Authors: Prashant Upadhyay; Rajib Kar; Durbadal Mandal; Sakti Prasad Ghoshal

Addresses: Department of ECE, National Institute of Technology, Durgapur, West Bengal 713209, India ' Department of ECE, National Institute of Technology, Durgapur, West Bengal 713209, India ' Department of ECE, National Institute of Technology, Durgapur, West Bengal 713209, India ' Department of EE, National Institute of Technology, Durgapur, West Bengal 713209, India

Abstract: This paper focuses on the design of low power and stable, novel 12T multi-threshold CMOS (MTCMOS)-based static random access memory (SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines. Reduction in swing voltage reduces the dynamic power dissipation. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep-to-active (OFF-to-ON condition) and active-to-sleep (ON-to-OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. So in the proposed SRAM cell both dynamic and static powers have been reduced. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. The circuit simulation has been done in 45 nm CMOS environment. Microwind 3.1 is used for the purpose of schematic and layout designs.

Keywords: multi-threshold CMOS; charge recycling; charge sharing; dynamic power; swing voltage; static power dissipation; low power cells; low leakage cells; SRAM cells; static RAM; random access memory.

DOI: 10.1504/IJCAET.2017.084901

International Journal of Computer Aided Engineering and Technology, 2017 Vol.9 No.3, pp.307 - 323

Received: 09 Sep 2014
Accepted: 07 Nov 2014
Published online: 09 Jul 2017 *

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Title: A 12T MT-CMOS low power and low leakage SRAM cell

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