Title: Hardware design of parallel switch setting algorithm for Benes networks

Authors: Yikun Jiang; Mei Yang

Addresses: Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, NV 89154, USA ' Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, NV 89154, USA

Abstract: Benes/Clos networks have been used in many areas, such as interconnection network in parallel computers, multiprocessors system, and networks-on-chip. The parallel switch setting algorithm is the key to satisfy the requirements of high performance switching networks. The Lee's routing algorithm is by far the most efficient parallel routing algorithm for Benes networks. However, there is no hardware implementation for this algorithm. In this paper, the Lee's routing algorithm is fully implemented in RTL and synthesised. We have refined the algorithm in data structure and initialisation/updating of relation values to make it suitable for hardware implementation. The simulation and synthesis results of the switching setting circuits for 4 × 4 to 64 × 64 Benes networks confirm that the timing, area, and power consumption of the circuit is consistent with the complexity of the Lee's algorithm. To the best of our knowledge, this is the first complete hardware implementation of the parallel switch setting algorithm which can handle all types of permutations including partial ones.

Keywords: Benes; parallel algorithm; hardware; RTL; implementation; synthesis.

DOI: 10.1504/IJHPSA.2017.083645

International Journal of High Performance Systems Architecture, 2017 Vol.7 No.1, pp.26 - 40

Received: 30 Mar 2016
Accepted: 25 Oct 2016

Published online: 13 Apr 2017 *

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